Browsing by Author "Pace, Calogero"

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Classification models and algorithms in application of multi-sensor systems to detection and identification of gases
(2014-06-04) Khalaf, Walaa; Cocurullo, Giuseppe; Gaudosio, Manlio; Pace, Calogero
The objective of the thesis is to adopt advanced machine learning tech- niques in the analysis of the output of sensor systems. In particular we have focused on the SVM (Support Vector Machine) approach to classi- ¯cation and regression, and we have tailored such approach for the area of sensor systems of the "electronic nose" type. We designed an Electronic Nose (ENose), containing 8 sensors, 5 of them being gas sensors, and the other 3 being a Temperature, a Humidity, and a Pressure sensor, respectively. Our system (Electronic Nose) has the ability to identify the type of gas, and then to estimate its concentration. To identify the type of gas we used as classi¯cation and regression technique the so called Support Vector Machine (SVM) approach, which is based on statistical learning theory and has been proposed in the broad learning ¯eld. The Kernel methods are applied in the context of SVM, to improve the classi¯cation quality. Classi¯cation means ¯nding the best divider (separator) between two or more di®erent classes without or with minimum number of errors. Many methods for pattern recognition or classi¯cation are based on neural network or other complex mathematical models. In this thesis we describe the hardware equipment which has been designed and implemented. We survey the SVM approach for machine learning and report on our experimentation.
Investigation of dimensionality e ects on capacitorless memory and trench power MOSFET
(2011-12-19) Pierro, Silvio; Falcone, Giovanni; Pace, Calogero; Sindona, Antonello
This thesis has dealt with two di erent problems solved with electronic device simulations (TCAD). The rst relates to the Trench power MOSFET device characterization, with particular attention to device breakdown voltage as a function of the device parameters. The second one is about the simulation of Zero capacitor DRAM devices. The trench structure analysis requires the use of a device simulator that implements the drift-di usion model with impact ionization model. For a better analysis results, the Trench structure is compared with the equivalent pn structure which shows similar trends in breakdown voltage, but slightly higher, due to the of the trench structure's absence that introduces an additional electric eld component anticipating the breakdown. For reference structure, the breakdown voltage depends only on drift region doping and length. Turning to Trench structure it can be noted that each Trench's shape parameter a ects the breakdown voltage, in particular: The distance between two structures in the trench does not a ect the calculation of the breakdown voltage. The Trench curvature radius and the oxide thickness are directly proportional to the breakdown voltage. The Trench width does not a ect the breakdown voltage. The trench length is the most important trench's parameter in order to evaluate a good model. A one-dimensional analytical model for pn structure has been presented using a maximum electrical eld value prediction as border condition for Poisson equation. The same model has been used for trench MOS devices using a correction factor for maximum electrical eld calculation based on trench penetration into drain region and on drain region length. The analytical model shows good results in comparison with simulation results for wide range simulations. For the Zero capacitor DRAM simulations, so called ZRAM devices, we have presented a simulation study aimed at understanding the operation mode, the potential performance in terms of READ sensitivity, programming windows and retention time, and the scalability of a double gate type II Z RAM cell with respect to the type I cells. We nd that the operations of a type II ZRAM cell can be implemented by changing simultaneously all electrode potentials and does not necessarily require an appropriate time sequence of bias voltages. Moreover, in the proposed operation mode, the excess charge is stored at the gate interfaces and not in the bulk body. This excess charge is a self consistent charge, created during the WRITE \1" phase by impaction ionization and BTBT at the drain side and de ned by the accumulation condition imposed by the gate bias during the HOLD phase. The independence of the stored charge on the particular WRITE \1" bias con guration allows an excellent determination and tuning of device performances by experiments and device simulations. Stored data is read by an asymmetrical bias con guration of the gate interfaces where the bottom gate interface works in a manner similar to the HOLD mode while the top gate interface works in a manner similar to the WRITE \1" mode but with a lower drain bias in order to avoid drain disturbs. The charge eventually stored at the bottom interface increases the bulk potential at the top interfaces which in order reduces the source-bulk energy barrier allowing a high READ current. Because of the exponential dependence of the READ current respect to the bulk potential a higher I1=I0 ratio is found respect to type I operation mode allowing higher READ sensitivity, programming windows and retention times. Data retention is limited by the leakage associated to the state \0" due to BTBT at the source/drain to bulk junctions. Except for device geometries with degraded SCEs (L<
Neutron induced single event burnout on power mosfets
(2014-11-17) Giordano, Carlo; Pantano, Pietro; Pace, Calogero
New methodologies and instrumentations for power semiconductor devices testing
(2016-02-02) Hernandez Ambato, Jorge Luis; Pantano, Pietro; Pace, Calogero; Fragomeni, Letizia
Nowadays electronic applications involve a high density of power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) which represent the major percentage of energy flow to be controlled. Moreover, new technologies, such as Silicon Carbide (SiC), have been well involved in the existing power applications. Therefore, the reliability of power devices is highly demanded. Since decades, a widely used accelerated test to evaluate the reliability of MOSFETs is the so-called High Temperature Reverse Bias (HTRB). In this stress test, the Devices Under Test (DUTs) are reverse polarized at a certain percentage of the rated breakdown voltage and maintained in this condition at high temperature for a determined long time. A typical HTRB test also incorporates Electrical Characterization Tests (ECTs) of DUTs before and after each stress period, seeking for failed devices. However, time elapsed between ECTs are long and degradation and failure information of DUTs might not be registered. In this context, an advanced methodology for HTRB test is proposed. The latter consists of applying more stress cycles of short duration together with more frequent ECTs at a relatively high temperature that can be directly compared to that of normal operation in power applications (i. e. 125 °C). With this methodology, more detailed information about degradation trends in electrical parameters, time of failures and stopping of stress test on degrading devices before full breakdown can be performed. The latter can be very useful in R&D stages, where the post-failure analysis of well-degraded devices, but not broken, is important. An automatized instrumentation, aimed to apply this methodology, has been implemented. The latter utilizes individual Thermal Control Modules (TCMs) to control the test temperature per single DUT. The temperature control is performed through an opposite mini-heater and firmware running on an 8-bit microcontroller. TCMs can be set remotely to apply test temperatures in the range [30-200 °C]. In addition, Switch Matrix Modules (SSMs) are implemented to configure the electrical connections required for HTRB or ECT tests remotely. A PC application controls all the modules through a Master Communication Module (MCM) also implemented. A commercial Source and Measure Unit (SMU) is used for the electrical stress. Full customization of HTRB and ECTs test parameters can be performed to optimize the stress and degradation data acquisition. Combining the advanced methodology and instrumentation above mentioned, more stressful conditions can be applied to shorten the overall test time without losing the electrical degradation trends of failing devices. In fact, features of the implemented instrumentation allow for controlling unbeneficial thermal runaway process on the single device, isolating thermal and electric of degraded devices, acquiring frequently electrical parameters data, performing ECTs at a relatively high temperature between shorter stress cycles, managing real-time control of HTRB test. These features are useful to get reliability data in a shorter time than a typical application of HTRB tests while preserving DUTs for post-failure analysis. The advanced methodology and automatized instrumentation have been applied to Si and SiC power MOSFETs with interesting results, demonstrating to be suitable for both shorter and more accelerated HTRB tests to acquire critical information necessary for the study of degradation processes and reliability in power devices. Moreover, results have demonstrated that degradation trends are not affected when more frequent ECTs at slightly different temperature are performed in the DUTs. In addition, accurate test results have shown that drawbacks of typical HTRB implementation have been solved through the advanced methodology and instrumentation reported. Complementing the work presented, Low-Frequency Noise Measurements (LFNMs) were also applied as valuable tool to investigate the degradation process in power MOSFETs after stressing them through HTRB test. A correlation between the results from advanced HTRB test and LFNM in power MOSFETs demonstrates that the electrical degradation is represented by a noise spectrum different to that for intrinsic 1/f noise.
Random telegraph signal in CMOS single photon avalanche diodes
(2019-05-21) Fiore, Daniela; Critelli, Salvatore; Pace, Calogero; Crupi, Felice; Di Capua, Francesco; Tomarchio, Elio Angelo
This dissertation is focused on single photon devices that have triggered a real revolution in the world of imaging, the Single Photon Avalanche Diodes (SPADs). These devices acquired immediately a great interest in the field of single photon imaging, since they showed great performances in several fields, such as quantum mechanics, optical fibres, fluorescent decays and luminescence in physics, chemistry, biology, medical imaging, etc. These applications require single photon detectors able to assure high performances in photon counting, such as high photon detection efficiency, high speed and extremely low noise detection. The interest on SPAD became wider as they have been implemented in Complementary Metal-Oxide Semiconductor (CMOS) technology, reaching the integration of quenching and post-processing circuits on the pixel itself. The high timing and spatial resolution, the low power performance, the easy integration of circuits made CMOS SPADs the best choice in the field of single photon detectors. The ability to detect individual photons with very high timing resolution, at the order of few tens of picoseconds, and with an internal gain of 106 allowed to reduce the complexity in amplification circuit. However, SPAD performance is also influenced by Dark Count Rate (DCR), i.e. no-photon induced count rate, and by Random Telegraph Signal (RTS) occurrence, i.e. DCR discrete fluctuations. DCRs are mainly due to defects introduced in the semiconductor lattice and in the oxide during the fabrication process. In addition, radiation environment can induce new defects in the silicon structure, knows as radiation-induced defects. These defects or cluster of defects create new energy levels in the bandgap and cause the generation of carriers in depletion regions through thermal processes (Shockley Read-Hall, SRH, processes) and tunneling processes. This results in the increase of the mean dark current and in RTS. An increased occurrence of RTS effects degrades the performances of the devices, since the randomisation of this signal makes impossible to calibrate correctly the device. Therefore, it is important to investigate RTS behaviour and recognize the defects involved in this mechanism. The identification of defects responsible for RTS and the understanding of its evolution could be very useful to limit the effects on the devices operating in radiation environment. The thesis is structured in four chapters. The first chapter introduces the semiconductor-based photodetectors, the evolution of these devices until to CMOS Single-Photon Counting Detectors (SPADs). SPADs are described in detail, by explaining the working principle and the associated electronic circuits. SPAD performances are also discussed, taking into consideration the crosstalk and afterpulse. The second chapter explains the mechanisms responsible for DCR increase and RTS occurrence, focusing on generated electron-hole pairs due to thermal trap-assisted transition or to trap-assisted tunnelling (TAT) and band-to-band tunnelling (BTBT) at high electric field. RTS phenomenon is described and several theoretical models to explain its origin are presented in this chapter. The third chapter describes SPADs device investigated in the experimental analysis, focusing on two different layouts implemented in the test-chip: P+/Nwell and Pwell/Niso layout. The experimental setup and SPAD characterization before irradiation is reported. The fourth chapter describes the proton irradiation test and presents the experimental RTS data and the evolution in frequency and time domain. The chapter reports also the experimental results obtained by RTS investigation on two different SPAD layouts. The results allowed to hypothesize an explanation involved in RTS phenomenon.