Tesi di Dottorato

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Author: search.filters.author.Crupi, FeliceStart date: 2001

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    Enhanced electromagnetic models for the accurate design of non-invasive microwave biosensors
    (Università della Calabria, 2020-04-27) Cioffi, Vincenzo; Crupi, Felice; Costanzo, Sandra
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    Methodologies and Applications for Big Data Analytics
    (Università della Calabria, 2020-05-02) Cassavia, Nunziato; Crupi, Felice; Flesca, Sergio; Masciari, Elio
    Due to the emerging Big Data paradigm, driven by the increase availability of users generated data, traditional data management techniques are inadequate in many real life scenarios. The availability of huge amounts of data pertaining to user social interactions calls for advanced analysis strategies in order to extract meaningful information. Furthermore, heterogeneity and high speed of user generated data require suitable data storage and management and a huge amount of computing power. This dissertation presents a Big Data framework able to enhances user quest for information by exploiting previous knowledge about their social environment. Moreover an introduction to Big Data and NoSQL systems is provided and two basic architecture for Big Data analysis are presented. The framework that enhances user quest, leverages the extent of influence that the users are potentially subject to and the influence they may exert on other users. User influence spread, across the network, is dynamically computed as well to improve user search strategy by providing specific suggestions, represented as tailored faceted features. The approach is tested in an important application scenario such as tourist recommendation where several experiment have been performed to assess system scalability and data read/write efficiency. The study of this system and of advanced analysis on Big Data has shown the need for a huge computing power. To this end an high performance computing system named CoremunitiTM is presented. This system represents a P2P solution for solving complex works by using the idling computational resources of users connected to this network. Users help each other by asking the network computational resources when they face high computing demanding tasks. Differently from many proposals available for volunteer computing, users providing their resources are rewarded with tangible credits. This approach is tested in an interesting scenario as 3D rendering where its efficiency has been compared with "traditional" commercial solutions like cloud platforms and render farms showing shorter task completion times at low cost.
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    Methodologies and Applications for Big Data Analytics
    (Università della Calabria, 2020-05-02) Cassavia, Nunziato; Crupi, Felice; Flesca, Sergio; Masciari, Elio;
    Due to the emerging Big Data paradigm, driven by the increase availability of users generated data, traditional data management techniques are inadequate in many real life scenarios. The availability of huge amounts of data pertaining to user social interactions calls for advanced analysis strategies in order to extract meaningful information. Furthermore, heterogeneity and high speed of user generated data require suitable data storage and management and a huge amount of computing power. This dissertation presents a Big Data framework able to enhances user quest for information by exploiting previous knowledge about their social environment. Moreover an introduction to Big Data and NoSQL systems is provided and two basic architecture for Big Data analysis are presented. The framework that enhances user quest, leverages the extent of influence that the users are potentially subject to and the influence they may exert on other users. User influence spread, across the network, is dynamically computed as well to improve user search strategy by providing specific suggestions, represented as tailored faceted features. The approach is tested in an important application scenario such as tourist recommendation where several experiment have been performed to assess system scalability and data read/write efficiency. The study of this system and of advanced analysis on Big Data has shown the need for a huge computing power. To this end an high performance computing system named CoremunitiTM is presented. This system represents a P2P solution for solving complex works by using the idling computational resources of users connected to this network. Users help each other by asking the network computational resources when they face high computing demanding tasks. Differently from many proposals available for volunteer computing, users providing their resources are rewarded with tangible credits. This approach is tested in an interesting scenario as 3D rendering where its efficiency has been compared with "traditional" commercial solutions like cloud platforms and render farms showing shorter task completion times at low cost.
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    Dynamic argumentation in artificial intelligence
    (Università della Calabria, 2020-04-20) Alfano, Gianvincenzo; Crupi, Felice; Greco, Sergio; Parisi, Francesco
    L’argumentation è una tematica di grande rilievo che si è distinta nel vasto mondo dell’Intelligenza Artificiale. Un sistema di argomentazione, adottando un particolare framework, riesce a gestisce discussioni tra agenti software e prendere decisioni in maniera autonoma su temi per cui si sta argomentando. Stabilire il modo in cui le decisioni vengono prese corrisponde a stabilire una semantica di argomentazione. Tali semantiche, godono di un alto costo computazionale, e pertanto, a seguito dell’aggiunta di nuove argomentazioni, nasce il problema di dover ricalcolare le decisioni (chiamate estensioni) sull’intero framework aggiornato. Sebbene i limiti computazionali e gli algoritmi per la valutazione di framework di argomentazione sono stati largamente studiati in letteratura, queste ricerche si basano su framework di tipo statico, ovvero framework di argomentazione che non subiscono aggiornamenti, nonostante in pratica i sistemi di argomentazione modellino un processo altamente dinamico quale è l’argomentazione. Lo scopo di questa tesi è di produrre algoritmi incrementali efficienti che risolvano i problemi principali sia dell’argumentation astratta (i cui argomenti rappresentano entità astratte), sia nel framework di argomentazione strutturato Defeasible Logic Programming (DeLP), i cui argomenti hanno un’esplicita struttura poiché derivano da una knowledge-base (un programma DeLP) contenente fatti, regole certe (strict) e regole incerte (defeasible). Di fronte alle modifiche sul grafo sottostante (nel caso di argomentazione astratta) o sul programma DeLP (nel caso di argomentazione strutturata), estensioni precedentemente calcolate sono parzialmente riutilizzate al fine di evitarne il ricalcolo da zero. La tesi fornisce diversi contributi sia teorici che pratici. In particolare, dopo aver analizzato i concetti preliminari alla base dei principali frameworks di argomentazione astratta, nel Capitolo 3 viene proposto un approccio per il problema dell'enumerazione delle estensioni preferred e semi-stable di un framework di argomentazione astratto. Nel Capitolo 4 viene affrontato il problema del ricalcolo incrementale di un'estensione complete, preferred, grounded e stable per frameworks astratti. Fondamentalmente, dato un framework iniziale, una sua estensione ed un update, viene determinato l’insieme di argomenti influenzati dalla modifica, i quali costituiscono un sottoinsieme degli argomenti iniziali utili a determinare un framework ridotto su cui viene calcolata un'estensione. Combinando parte dell'estensione iniziale con quella calcolata sul framework ridotto, si ottiene un'estensione del framework aggiornato. Questo approccio viene esteso nel Capitolo 5 ai framework di argomentazione bipolari e con attacchi di secondo ordine, sfruttando una traduzione in framework astratti classici. Tale tecnica incrementale viene utilizzata nel Capitolo 6 per far fronte al calcolo incrementale dell’accettazione scettica di un argomento in accordo alla semantica preferred (ovvero stabilire se un argomento è contenuto in tutte le estensioni preferred), sfruttando la relazione tra le semantiche preferred e ideal. L’idea e le motivazioni alla base della tecnica incrementale proposta nel Capitolo 4 sono state sfruttate nel Capitolo 7 per affrontare il problema del ricalcolo incrementale dello stato dei letterali di un programma DeLP a seguito dell’aggiunta o rimozione di regole. Infatti, dopo aver mostrato che il problema risulta essere NP-hard, viene presentato un algoritmo incrementale basato su un ipergrafo che codifica le relazioni di dipendenza tra letterali sulla base delle regole che formano il programma DeLP, al fine di individuare la porzione del programma influenzata dalla modifica che necessita del ricalcolo. Tutti gli algoritmi proposti sono stati analizzati sperimentalmente, mostrando miglioramenti significativi rispetto al corrispondente calcolo da zero.
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    Distributed Model Predictive Control Strategies for Constrained Multi-Agent Systems Moving in Uncertain Environments
    (Università della Calabria, 2021-09-17) Babak, Rahmani; Franzè, Giuseppe; Crupi, Felice
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    Phased array building blocks for 5G networks
    (Università della Calabria, 2021-09-09) Scalise, Giuseppe; Crupi, Felice; Boccia, Luigi
    5G will have to support a multitude of new applications with a wide variety of requirements, including higher user data rates and network capacity, reduced latency, improved energy efficiency, and so on. These aspects will lead to a radical change in network architecture from different points of view. For example, the densification of small cells in the access network will produce massive traffic to the core network and an increment of the interference due to the lower inter-cell distance. In particular, millimeter waves (mm-waves) bands, due to their large unlicensed and lightly licensed bandwidths, have become a promising candidate for the next-generation wireless communications, to accommodate users demand for multi-Gbps data rates, but this will move the attention to the complexity and the criticality of the base station antenna systems. In fact, because of the carrier frequency increment, it will be necessary to use large-scale antennas to compensate channel losses which are significant in the millimeter wave bands. Furthermore, the combined use of phased arrays and massive MIMO technologies will be required to achieve a better usage of the radio channel, by implementing more accurate spatial selectivity techniques, thus resulting in an increased network capacity and signal-to-noise (SNR) performance. Among the spectrum portions used in the access segment, the Ka-band is the most interesting and attractive to implement low-cost wideband antenna systems with high steering capability along both azimuth and elevation directions and good performance in terms of directivity. On the other side, the shift to higher frequencies required by these systems will imply a decrease in the space available for the integration of the chip containing the transceiver and all the necessary RF circuitry. Therefore, hardware integration will be a key element to be taken into consideration for the development of the fifth-generation phased array systems. The main object of this work is to analyze and design different building blocks of phased array systems operating in Ka-band for 5G applications. The research activities presented in this dissertation can be summarized into two parts. In the first part, a 32-element dual-polarized array operating in n257 band (26.5-29.5 GHz) for 5G phased array systems is presented, where a novel ultra-low profile dual-polarized Magneto-Electric dipole has been employed as the radiating element. This array system has been thought to be used in a 5G small cell, where the radiated beam should be directed along azimuth and elevation considering the scan range (±55°𝐴𝑍,±20°𝐸𝐿) to increase both spatial selectivity and network capacity. In the second part, the attention has been focused on the study and the design of variable gain amplifiers (VGAs) in a standard 0.13 μm SiGe BiCMOS technology for 5G phased array applications. At first, the performance of a Ka-band conventional single-stage NMOS voltage variable attenuator (VVA) has been compared with a novel Ka-band hybrid single-stage VVA with improved power handling capability and linearity, where two shunt HBT transistors act as varistors to change continuously the attenuation state of the cell. At this point, a monolithically-integrated dual-stage VGA with higher power capability and wider gain tuning range based on the use of VVA circuit as control element has been developed. This component should be employed directly as an end-stage variable gain PA in Si-based 5G transmitters or as a driver in hybrid Si/GaN-based or Si/GaAs-based 5G transceivers.
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    Radianting elements for 5G Backhauling Systems
    (Università della Calabria, 2021-09-09) Mustacchio, Carmine; Crupi, Felice; Arnieri, Emilio
    5G will have to support a multitude of new applications with a wide variety of requirements, including higher peak and user data rates, reduced latency, enhanced indoor coverage, increased number of devices, and so on. These aspects will lead to a radical change in network architecture from different points of view. For example, the densification of small cells produces massive backhaul traffic in the core network, which inevitably becomes an important, but somewhat less addressed bottleneck in the system. In particular, millimeter waves (mm-waves) bands, due to their large unlicensed and lightly licensed bandwidths, have become a promising candidate for the next-generation wireless communications, to accommodate users demand for multi-Gbps data rates, but this will move the attention to the complexity, the criticality and the infrastructure costs of backhauling antennas. In fact, because of the losses produced by the increasing frequency, it will be necessary to use antennas with reconfigurable directional links and, where necessary, to enable the use of massive MIMO architectures. Among the spectrum portions, the E-band and W-band are the most interesting and attractive. In fact, the unlicensed frequencies in many geographic areas will allow to reduce the operators' costs at the same bit rate. Furthermore, the directive beam steering antennas will allow the capability of spectrum reuse in the same cell. However, there are different unresolved problems, due to the need to use antennas with electronic reconfigurable beam steering both in azimuth and elevation. The spread of this kind of radiator, on a large scale, will require, necessarily, the development of new antennas that will be able to reduce manufacturing and integration costs. The main object of this work is to investigate and develop different types of new antennas, which will be able to satisfy all backhauling systems requirements for 5G applications. The research activities presented in this dissertation can be summarized into three parts. In the first part, a beam-switched Cassegrain reflector antenna in E-band (71-86 GHz) for backhauling systems for 5G applications is presented, including the study of different feeding elements which will illuminate the double reflector system. This antenna has been thought to reconfigure the beam compensating small boom movements, which are estimated to be within ±1° in both azimuth and elevation planes. After evaluating all the possible solutions, an array of magneto-electric dipoles has been selected as feeding element for the E-band beam-switched Cassegrain antenna. In the second part, the attention has been focused on the study and the design of antennas on-chip (AoCs) in a standard 0.13 μm SiGe BiCMOS technology. In particular, two new techniques for enhancing the gain of on-chip monopole antennas in W-Band (75-110 GHz) are proposed. These new proposed methodologies involved the use of a new AMC (Artificial magnetic conductor), composed by some SRRs (Split ring resonators) and LBE (Localized Backside Etching), and some capacitively loaded SRRs. In the last part, a I/Q phase shifter design in E-band (71-86 GHz) in a SiGe BiCMOS 55 nm semiconductor technology is proposed. The proposed phase shifter is a sub-block of a compact E-band I/Q Receiver in SiGe BiCMOS for 5G backhauling applications.
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    Innovative Techniques to Support the Surveying and the Exploration of Underwater Sites by Scientific and Recreational Divers
    (Università della Calabria, 2021-05-14) Mangeruga, Marino; Crupi, Felice; Casavola, Alessandro; Bruno, Fabio; Pupo, Francesco
    In the submerged environment divers often suffer from low visibility conditions that make difficult the orientation within an underwater site. At present, there is a lack of technologies and tools supporting the divers to better orientate themselves in the underwater environment and to simplify their comprehension of the context. The research aims to design and develop innovative solutions to support divers, both recreative and technical/scientific ones, through a novel system for underwater navigation and exploration, providing them with underwater geo-localization, contextualized information, augmented reality (AR) contents and recommendation about the optimal path to follow during the dive. A first aspect on which the research work focused is the Underwater Image Enhancement. This study has led to the development of a software tool to enhance underwater images with well-known methods at the SoA. A benchmark of these well-known methods has been produced and some guidelines to evaluate the underwater image enhancement methods have been formulated. The effort of this part of the research has been to guide the community towards the definition of a more effective and objective methodology for the evaluation of underwater image enhancement methods. Another aspect of the research concerned the Underwater Navigation and Underwater AR (UWAR). A software for underwater tablets, namely Divy, has been designed and developed to support divers’ navigation and exploration. It enables the divers to access different features such as the visualization of a map of the underwater site that allows them to know their position within the submerged site, the possibility to acquire geo-localized data, the visualization of additional information about specific points of interest and the communication with the surface operators through an underwater messaging system. On this basis, the UWAR concept applied in Underwater Cultural Heritage sites has been designed and developed as well, consisting of an augmented visualization representing a hypothetical 3D reconstruction of the archaeological remains as they appeared in the past. The geo-localization is provided by an acoustic localization system, but this kind of technology suffers from a low update rate, and cannot be employed alone for the AR purpose. To improve the performance of the UWAR and provide the users with a smooth AR visualization, a hybrid technique that merges data from an acoustic localization system with data coming from a visual inertial-odometry framework has been conceived and developed to deliver positioning information with a higher update rate with respect to the acoustic system alone. In particular, given the low update rate of the acoustic system, a strategy has been implemented aimed to fill the gaps between two consecutive acoustic positioning data. User testing has been conducted to assess the effectiveness and potential of the developed UWAR technologies. Finally, an innovative approach to dive planning based on an original underwater pathfinding algorithm has been conceived. It computes the best 3D path to follow during the dive in order to maximise the number of Points of Interest (POIs) visited, while taking into account the safety limitations strictly related to scuba diving. This approach considers the morphology of the 3D space in which the dive takes place to compute the best path, taking into account the diving decompression limits and avoiding the obstacles through the analysis of a 3D map of the site.
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    Mining and learning problems in complex graph data
    (Università della Calabria, 2021-05-10) Mandaglio, Domenico; Crupi, Felice; Greco, Sergio; Tagarelli, Andrea
    I grafi sono modelli matematici che rappresentano oggetti, chiamati nodi o vertici, coinvolti in relazioni a coppia, detti archi. Tali modelli vengono impiegati per descrivere sistemi interconnessi tra cui reti tecnologiche (es. il World Wide Web), reti sociali e biologiche. A partire dal modello originario dei grafi, diverse estensioni del modello sono state proposte in letteratura: grafi pesati, multidimensionali, temporali e probabilistici permettono di esprimere, rispettivamente, l’intensità associata a ogni arco, rappresentare diverse tipologie di relazioni tra vertici, includere informazioni su quando le interazioni tra nodi avvengono, e assegnare a ogni possibile peso sugli archi la probabilità di osservare quello specifico peso. Lo scopo di questa tesi è definire modelli e metodi per problemi di mining e learning di relazioni forti e nascoste tra nodi su grafi complessi. In particolare, il focus di questo progetto di ricerca è la scoperta di relazioni a coppia come associazioni di gruppo e relazioni di trust. Il primo obiettivo consiste nel partizionare l’insieme dei nodi di un grafo in gruppi (detti cluster o community) tali che i nodi appartenenti allo stesso gruppo siano collegati più fortemente tra di loro rispetto che con il resto della rete. Questo obiettivo è anche noto in letteratura come graph clustering o community detection. Le community (o cluster) sono gruppi di entità che probabilmente condividono delle proprietà e/o hanno un ruolo simile all’interno del sistema a cui appartengono. Le relazioni di trust vengono tipicamente modellate attraverso un grafo pesato, detto rete di trust, che si riferisce a un grafo di individui collegati da relazioni di coppia asimmetriche corrispondenti a espressioni soggettive di fiducia, dove il peso associato a ogni arco viene interpretato come il grado di fiducia che un utente ha nei confronti di un altro individuo. Ogni modello di rappresentazione a grafo, indipendentemente dalla sua natura, permette di descrivere in diversi modi l’intrinseca natura multiforme dei sistemi reali che deve essere tenuta in considerazione quando si intende identificare relazioni tra i nodi come quelle di gruppo o di trust. Questo implica la necessità di un processo di aggregazione di informazioni che permette di considerare simultaneamente i diversi aspetti del sistema rappresentato. Tuttavia, l’aggregazione dei diversi aspetti di un sistema pone alcune problematiche aggiuntive al task considerato poiché le diverse dimensioni dei dati potrebbero essere inconsistenti tra di loro o l’informazione relativa a un qualche aspetto potrebbe rappresentare rumore per il raggiungimento dell’obiettivo prefissato. L’abbondanza e diversità di dati rappresentabili attraverso grafi che può essere estratta da sistemi online (es. il Web) o offline (es. interazioni sociali) favorisce la necessità di nuovi modelli e metodi che siano capaci di tenere in considerazione efficacemente l’eterogeneità nella tipologia di informazioni nella scoperta di pattern nel comportamento di entità appartenenti a un sistema complesso. Più specificatamente, quattro sono i temi di ricerca che possono essere indentificati in questa tesi. Primo, è stato studiato il problema di consensus community detection su reti multidimensionali: dato un insieme di partizionamenti dei nodi di una rete, ciascuno calcolato considerando separatamente una dimensione del grafo multidimensionale, trovare un nuovo partizionamento dei nodi (detto consensus clustering) che sia rappresentativo e, allo stesso tempo, filtri l’eventuale rumore dei vari partizionamenti in input. Come seconda linea di ricerca, è stato trattato il problema di consensus community detection dinamico su grafi temporali che consiste nel calcolare, per ogni stato di evoluzione di una rete, un consensus clustering che sia rappresentativo degli stati precedentemente osservati sulla rete e, quindi, rispecchi la sequenza delle strutture a community nei vari istanti di tempo. Chiaramente, la natura temporale di questo secondo problema pone alcune sfide aggiuntive nella sua risoluzione poiché i vari partizionamenti sono disponibili e devono essere processati in modo incrementale; inoltre, vi è il requisito che bisogna opportunamente pesare le informazioni sugli stati nella rete in modo da dare maggior rilievo agli stati più recenti piuttosto che quelli più remoti. Inoltre, la dimensione temporale delle interazioni tra utenti di una rete sociale può aiutare a inferire una rete di trust. Quest’ultimo obiettivo corrisponde alla terza linea di ricerca di questa tesi che ha come obiettivo la risoluzione del seguente problema: data una sequenza di grafi pesati corrispondenti agli stati di una rete in diversi istanti di tempo, derivare un grafo pesato e orientato, i cui nodi corrispondono alle entità del grafo temporale e gli archi rappresentano le relazioni di trust con associato grado di fiducia. Come quarta linea di ricerca è stato studiato un nuovo problema di clustering su grafi probabilistici in cui le interazioni tra i nodi sono caratterizzate da distribuzioni di probabilità e condizionate da fattori esterni ai nodi ma caratteristici dell’ambiente in cui interagiscono. Questo contesto include ogni scenario in cui una serie di azioni possono alterare le interazioni tra entità tra cui, ad esempio, i sistemi di raccomandazione su piattaforme di social media e task di team formation. In particolare, è stato considerato il caso in cui i fattori condizionanti le interazioni possono essere modellati attraverso un clustering dei nodi del grafo e l’obiettivo è trovare il clustering che massimizza l’interazione totale nel grafo. Per ciascuna linea di ricerca sono stati proposti degli algoritmi che sono stati confrontati, su dati reali e/o generati artificialmente, con lo stato dell’arte dei rispettivi problemi al fine di valutarne sia l’efficacia che l’efficienza.
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    Progettazione di circuiti a bassissima potenza e tensione per System on Chip energicamente autonomi
    (Università della Calabria, 2021-05-15) Fassio, Luigi; Crupi, Felice; Lanuzza, Marco
    Ultra-low power/voltage (ULP/ULV) circuits (both analog and digital blocks) have been gaining considerable interest from the scientific community in the last few years. The advent of the Internet of Things (IoT) era has also increased the interest of the market in ULP/ULV circuits addressed to energy-autonomous and extremely small-sized Systems-on-Chip (SoCs). Wireless sensor networks, biomedical implantable devices, wearable computing, ambient control intelligence, air quality monitoring, warehouse, and agriculture monitoring are just some of the fields that can benefit from ULP/ULV circuits. The design of ULP/ULV circuit blocks for energy-autonomous SoCs is a wide topic and needs some knowledge on several elements that can compose these SoCs. In this regard, this thesis first provides a general overview on energy-autonomous SoCs with a focus on available energy harvesting sources and energy storage solutions. The availability of on-chip energy harvesting/storage opens the route for the development of battery-less IoT sensor nodes and moves the challenge towards the design of ULP/ULV circuits that make the node working even with a small amount of available energy from harvesting. Among various key building blocks of SoCs, this thesis presents the design of voltage/current reference circuits to provide a precise and stable DC bias under a wide range of environmental conditions, a level shifter to interface blocks between different voltage domains, and comparators to interface the analog world with the digital one. More specifically, a low-area voltage reference circuit able to operate at supply voltage as low as 250 mV and 5.4 pW of power consumption at room temperature is first presented. The proposed circuit exploits a body biasing scheme to deal with the effect of voltage/temperature fluctuations and hence to ensure good accuracy of the generated output voltage, as demonstrated through measurements on a test chip fabricated in 180-nm CMOS technology. The design of a current reference circuit based on a voltage generator exploiting the structure used for the voltage reference is also presented and validated by means of silicon measurements on a 180-nm prototype. The proposed circuit properly works down to 0.6 V to generate a current in the nA range with only 4,000-μm2 area occupancy, while reaching high power efficiency as guaranteed by the pW-power consumption of the voltage generator sub-block. Then, the design of a global variation-aware voltage reference based on an on-chip process sensor is proposed with the aim of achieving low sensitivity to process variations and overall good accuracy against process-voltage-temperature (PVT) variations, while also ensuring ULP/ULV operation, i.e., minimum supply voltage of 200 mV and power consumption of only 3.2 pW at room temperature. Experimental results in 180-nm CMOS technology across corner wafers demonstrate the effectiveness of the proposed solution. In addition, the design of a robust level shifter able to convert input voltages from the subthreshold regime (around 100 mV) up to the nominal supply voltage (1.8 V) is presented. The proposed circuit is based on a self-biased low-voltage cascode current mirror topology that features diode-connected PMOS and NMOS transistors to drive the split-input inverting buffer used as output stage with high energy efficiency. Obtained measurement results in 180-nm CMOS technology and across corner wafers demonstrate good robustness and performance of the proposed level shifter as compared to prior art. Finally, the design of an ULP/ULV comparator is proposed by using the dynamic leakage suppression (DLS) logic family. In particular, two different topologies, i.e., a single-stage structure and a dual-stage architecture based on the combination of two single-stage comparator are presented and validated through silicon measurements on 180-nm test chips, which demonstrate a power consumption of few tens of pW. My research activity during PhD concerned the design of innovative ULP/ULV circuits and their validation through silicon measurements. First, a low-area voltage reference circuit able to operate at supply voltage as low as 250 mV and 5.4 pW of power consumption at room temperature was designed and fabricated in 180-nm CMOS technology. The proposed circuit exploits a body biasing scheme to deal with the effect of voltage/temperature fluctuations and hence to ensure good accuracy of the generated output voltage. A current reference circuit based on a voltage generator exploiting the structure used for the voltage reference was also designed and validated by means of silicon measurements on a 180-nm prototype. The proposed current reference properly works down to 0.6 V to generate a current in the nA range with only 4,000-μm2 area occupancy, while reaching high power efficiency as guaranteed by the pW-power consumption of the voltage generator sub-block. Then, the design of a global variation-aware voltage reference based on an on-chip process sensor was realized with the aim of achieving competitive sensitivity to process variations and and overall accuracy against process-voltage-temperature (PVT) variations, while also ensuring ULP/ULV operation (minimum supply voltage of 200 mV and power consumption of only 3.2pW at room temperature). Experimental results in 180-nm CMOS technology across corner wafers demonstrate the effectiveness of the proposed solution. The research activity was also addressed to interfacing blocks between different voltage domains in multiple-voltage systems. In this regard, a robust level shifter able to convert input voltages from the subthreshold regime (around 100 mV) up to the nominal supply voltage (1.8 V) was designed. The proposed circuit is based on a self-biased low-voltage cascode current mirror topology that features diode-connected PMOS and NMOS transistors to drive the split-input inverting buffer used as output stage with high energy efficiency. Obtained measurement results in 180-nm CMOS technology and across corner wafers demonstrate good robustness and performance of the proposed level shifter as compared to prior art. Finally, to interface the analog world with the digital one, an ULP/ULV comparator was designed by using the dynamic leakage suppression (DLS) logic family. Two different topologies, i.e., a single-stage structure and a dual-stage architecture based on the combination of two single-stage comparator were fabricated and validated through silicon measurements on 180-nm test chips, which demonstrated a power consumption of few tens of pW.