Tesi di Dottorato
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Item Innovative Techniques to Support the Surveying and the Exploration of Underwater Sites by Scientific and Recreational Divers(Università della Calabria, 2021-05-14) Mangeruga, Marino; Crupi, Felice; Casavola, Alessandro; Bruno, Fabio; Pupo, FrancescoIn the submerged environment divers often suffer from low visibility conditions that make difficult the orientation within an underwater site. At present, there is a lack of technologies and tools supporting the divers to better orientate themselves in the underwater environment and to simplify their comprehension of the context. The research aims to design and develop innovative solutions to support divers, both recreative and technical/scientific ones, through a novel system for underwater navigation and exploration, providing them with underwater geo-localization, contextualized information, augmented reality (AR) contents and recommendation about the optimal path to follow during the dive. A first aspect on which the research work focused is the Underwater Image Enhancement. This study has led to the development of a software tool to enhance underwater images with well-known methods at the SoA. A benchmark of these well-known methods has been produced and some guidelines to evaluate the underwater image enhancement methods have been formulated. The effort of this part of the research has been to guide the community towards the definition of a more effective and objective methodology for the evaluation of underwater image enhancement methods. Another aspect of the research concerned the Underwater Navigation and Underwater AR (UWAR). A software for underwater tablets, namely Divy, has been designed and developed to support divers’ navigation and exploration. It enables the divers to access different features such as the visualization of a map of the underwater site that allows them to know their position within the submerged site, the possibility to acquire geo-localized data, the visualization of additional information about specific points of interest and the communication with the surface operators through an underwater messaging system. On this basis, the UWAR concept applied in Underwater Cultural Heritage sites has been designed and developed as well, consisting of an augmented visualization representing a hypothetical 3D reconstruction of the archaeological remains as they appeared in the past. The geo-localization is provided by an acoustic localization system, but this kind of technology suffers from a low update rate, and cannot be employed alone for the AR purpose. To improve the performance of the UWAR and provide the users with a smooth AR visualization, a hybrid technique that merges data from an acoustic localization system with data coming from a visual inertial-odometry framework has been conceived and developed to deliver positioning information with a higher update rate with respect to the acoustic system alone. In particular, given the low update rate of the acoustic system, a strategy has been implemented aimed to fill the gaps between two consecutive acoustic positioning data. User testing has been conducted to assess the effectiveness and potential of the developed UWAR technologies. Finally, an innovative approach to dive planning based on an original underwater pathfinding algorithm has been conceived. It computes the best 3D path to follow during the dive in order to maximise the number of Points of Interest (POIs) visited, while taking into account the safety limitations strictly related to scuba diving. This approach considers the morphology of the 3D space in which the dive takes place to compute the best path, taking into account the diving decompression limits and avoiding the obstacles through the analysis of a 3D map of the site.Item Progettazione di circuiti a bassissima potenza e tensione per System on Chip energicamente autonomi(Università della Calabria, 2021-05-15) Fassio, Luigi; Crupi, Felice; Lanuzza, MarcoUltra-low power/voltage (ULP/ULV) circuits (both analog and digital blocks) have been gaining considerable interest from the scientific community in the last few years. The advent of the Internet of Things (IoT) era has also increased the interest of the market in ULP/ULV circuits addressed to energy-autonomous and extremely small-sized Systems-on-Chip (SoCs). Wireless sensor networks, biomedical implantable devices, wearable computing, ambient control intelligence, air quality monitoring, warehouse, and agriculture monitoring are just some of the fields that can benefit from ULP/ULV circuits. The design of ULP/ULV circuit blocks for energy-autonomous SoCs is a wide topic and needs some knowledge on several elements that can compose these SoCs. In this regard, this thesis first provides a general overview on energy-autonomous SoCs with a focus on available energy harvesting sources and energy storage solutions. The availability of on-chip energy harvesting/storage opens the route for the development of battery-less IoT sensor nodes and moves the challenge towards the design of ULP/ULV circuits that make the node working even with a small amount of available energy from harvesting. Among various key building blocks of SoCs, this thesis presents the design of voltage/current reference circuits to provide a precise and stable DC bias under a wide range of environmental conditions, a level shifter to interface blocks between different voltage domains, and comparators to interface the analog world with the digital one. More specifically, a low-area voltage reference circuit able to operate at supply voltage as low as 250 mV and 5.4 pW of power consumption at room temperature is first presented. The proposed circuit exploits a body biasing scheme to deal with the effect of voltage/temperature fluctuations and hence to ensure good accuracy of the generated output voltage, as demonstrated through measurements on a test chip fabricated in 180-nm CMOS technology. The design of a current reference circuit based on a voltage generator exploiting the structure used for the voltage reference is also presented and validated by means of silicon measurements on a 180-nm prototype. The proposed circuit properly works down to 0.6 V to generate a current in the nA range with only 4,000-μm2 area occupancy, while reaching high power efficiency as guaranteed by the pW-power consumption of the voltage generator sub-block. Then, the design of a global variation-aware voltage reference based on an on-chip process sensor is proposed with the aim of achieving low sensitivity to process variations and overall good accuracy against process-voltage-temperature (PVT) variations, while also ensuring ULP/ULV operation, i.e., minimum supply voltage of 200 mV and power consumption of only 3.2 pW at room temperature. Experimental results in 180-nm CMOS technology across corner wafers demonstrate the effectiveness of the proposed solution. In addition, the design of a robust level shifter able to convert input voltages from the subthreshold regime (around 100 mV) up to the nominal supply voltage (1.8 V) is presented. The proposed circuit is based on a self-biased low-voltage cascode current mirror topology that features diode-connected PMOS and NMOS transistors to drive the split-input inverting buffer used as output stage with high energy efficiency. Obtained measurement results in 180-nm CMOS technology and across corner wafers demonstrate good robustness and performance of the proposed level shifter as compared to prior art. Finally, the design of an ULP/ULV comparator is proposed by using the dynamic leakage suppression (DLS) logic family. In particular, two different topologies, i.e., a single-stage structure and a dual-stage architecture based on the combination of two single-stage comparator are presented and validated through silicon measurements on 180-nm test chips, which demonstrate a power consumption of few tens of pW. My research activity during PhD concerned the design of innovative ULP/ULV circuits and their validation through silicon measurements. First, a low-area voltage reference circuit able to operate at supply voltage as low as 250 mV and 5.4 pW of power consumption at room temperature was designed and fabricated in 180-nm CMOS technology. The proposed circuit exploits a body biasing scheme to deal with the effect of voltage/temperature fluctuations and hence to ensure good accuracy of the generated output voltage. A current reference circuit based on a voltage generator exploiting the structure used for the voltage reference was also designed and validated by means of silicon measurements on a 180-nm prototype. The proposed current reference properly works down to 0.6 V to generate a current in the nA range with only 4,000-μm2 area occupancy, while reaching high power efficiency as guaranteed by the pW-power consumption of the voltage generator sub-block. Then, the design of a global variation-aware voltage reference based on an on-chip process sensor was realized with the aim of achieving competitive sensitivity to process variations and and overall accuracy against process-voltage-temperature (PVT) variations, while also ensuring ULP/ULV operation (minimum supply voltage of 200 mV and power consumption of only 3.2pW at room temperature). Experimental results in 180-nm CMOS technology across corner wafers demonstrate the effectiveness of the proposed solution. The research activity was also addressed to interfacing blocks between different voltage domains in multiple-voltage systems. In this regard, a robust level shifter able to convert input voltages from the subthreshold regime (around 100 mV) up to the nominal supply voltage (1.8 V) was designed. The proposed circuit is based on a self-biased low-voltage cascode current mirror topology that features diode-connected PMOS and NMOS transistors to drive the split-input inverting buffer used as output stage with high energy efficiency. Obtained measurement results in 180-nm CMOS technology and across corner wafers demonstrate good robustness and performance of the proposed level shifter as compared to prior art. Finally, to interface the analog world with the digital one, an ULP/ULV comparator was designed by using the dynamic leakage suppression (DLS) logic family. Two different topologies, i.e., a single-stage structure and a dual-stage architecture based on the combination of two single-stage comparator were fabricated and validated through silicon measurements on 180-nm test chips, which demonstrated a power consumption of few tens of pW.Item Study characterization of modern 4h-sic power mosfetsF(Università della Calabria, 2021-05-05) Cosentino, Giuseppe; Crupi, FeliceItem Emering problems in influence propagation and maximization(Università della Calabria, 2021-05-10) Caliò, Antonio; Crupi, Felice; Tagarelli, AndreaIn the last two decades we witnessed the advent and the rapid growth of online social networks (OSNs). The impact of their pervasive diffusion on everyday life has been dramatic. In fact, social networks changed the way we interact with each other, the way we access information and the way companies engage with their audience or customers. A major consequence of the broad adoption and diffusion of social networks is the availability of an unprecedented amount of user data, which enables the opportunity for social and network scientists to investigate and observe many facets of human behaviors. Arguably, one of the most interesting facet is related to the notion of social influence. Following this observation, this research project is mainly centered around the concept of social influence, specifically its propagation and maximization. Therefore, the goal of this thesis is twofold. To begin with, we investigate the complexity of influence propagation in real-world contexts. This leads to the definition of a novel class of diffusion models. Such models represent an attempt to unify, under a well-defined framework, all the aspects that contribute to the inherent complexity of any influence propagation phenomena. Afterwards, we devote our attention to the influence maximization problem. To this purpose, we first provide a detailed characterization of social influence from a topological perspective. Specifically, we want to understand if and to what extent being a good spreader depends on being located into strategic regions of a network. Finally, we focus on the application of the influence maximization problem. In particular, we address a variant of the original problem, which is especially suitable for viral marketing scenarios. To this end, we propose two different diversity-sensitive targeted influence maximization problems. Both proposals share a common intent, which is assessing the benefit of embedding a notion of diversity into the process of the seeds identification. Nonetheless, diversity is considered from two different perspectives: (i) as a function of the topological properties of the nodes; (ii) as a function of some categorical data available on the node level.